Latch-up Prevention in Merged Bipolar-MOS Structures for BiCMOS Applications
نویسندگان
چکیده
BiCMOS technology [1] offers both the high driving capability of bipolar devices and the high input impedance of CMOS devices. The potential of BiCMOS technology has been demonstrated in a variety of applications such as gate arrays [2], static RAMs [3], dynamic RAMs [4] and microprocessors [5]. One of drawbacks of the conventional BiCMOS process is that the integration density is rather low since the MOS and bipolar devices are built in separate islands and interconnected externally. Furthermore, parasitic interconnect capacitance and resistance may cause substantial delay during transient operation. To overcome these problems, the use of physically merged bipolar-MOS devices in the implementation of BiCMOS circuits have been proposed [6-10]. Fig. 1 shows a complementary BiCMOS inverter circuit. The pull-up and pull-down transistors are a merged PMOS and NPN structure (BiPMOS) and a merged NMOS and PNP structure (BiNMOS).
منابع مشابه
A New True-Single-Phase-Clocking BiCMOS Dynamic Pipelined Logic Family for High-Speed, Low-Voltage P - Solid-State Circuits, IEEE Journal of
New true-single-phase-clocking (TSPC) BiCMOS/ BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic...
متن کاملA 16-GHz Ultra-High-Speed Si–SiGe HBT Comparator
This paper presents an improved master–slave bipolar Si–SiGe HBT comparator design for ultra-high-speed data converter applications. The latch is maintained during the track stage facilitating quick transition back to the latch stage, increasing the sampling speed of the comparator. Implemented in a 0.5m 55-GHz BiCMOS Si–SiGe process, this comparator consumes approximately 80 mW with sampling s...
متن کاملA 4-ns 4K 1-bit two-port BiCMOS SRAM
T’fris paper introduces a two-port BiCMOS static memory cell that combines ECL-level word-linevoltageswingsandemitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access (CSEA) cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAM’S while preserving the high density and low power...
متن کاملMicrosupercomputers : Design and Implementation Stanford University Computer Systems Laboratory Technical Progress Report
This paper introduces a two-port BiCMOS static mem-ory cell that combines ECL level word-line voltage swings andemitter-follower bit line coupling with a static CMOS latchto achieve access times comparable to those of high-speedbipolar SRAM's, while preserving the high density and lowpower of CMOS memory arrays. The memory can be ac-cessed for read and write independentl...
متن کاملMICROSUPERCOMPUTERS: DESIGN AND IMPLEMENTATION 7, AUTHGRIsl
This paper introduces a two-port BiCMOS static mem-ory cell that combines ECL level word-line voltage swings andemitter-follower bit line coupling with a static CMOS latchto achieve access times comparable to those of high-speedbipolar SRAM's, while preserving the high density and lowpower of CMOS memory arrays. The memory can be ac-cessed for read and write independentl...
متن کامل